kravietz 🦇 @kravietz@social.privacytools.io

**Many mosques in India turned into COVID centres amid virus surge**

"Many mosques across India have opened their doors for COVID patients as the second wave overwhelms hospitals."

https://www.aljazeera.com/news/2021/5/10/places-of-worship-try-to-help-indians-deal-with-covid-19-crisis

#news #bot

More BBC guff about how wonderful it is to commute again

#nuclear #nucleare #meme #memes #funny #energiewende #renewables #nuclear #nucleare #rinnovabili #ambiente #energianucleare #nuclearpower #nuclearenergy #ambientalismo @OCRbot

Managed to get to the polling station at just after 21:30, was working in Cambridge today so decided to visit later in the evening on the way back..

This is way less hassle than going earlier, there were 0 other people (none of the political campaigners you often get earlier in the day), and plenty of parking space (I wouldn't normally drive to the polling station as its within 0,5km of my house but was going home in that direction anyway)

“Data protection by design” fail?

QT RachelTobac: Huge heads up on PayPal Twitter Tip Jar. If you send a person a tip using PayPal, when the receiver opens up the receipt from the tip you sent, they get your *address*. Just tested to confirm by tipping @yashar on Twitter w/ PayPal and he did in fact get my address I tipped him. https://twitter.com/twittersupport/status/1390396738788339722

On 9 August hundreds of people participated in fight against police in #Pinsk town south of #Belarus starting uprising in their town against dictatorship. 14 of those people were identified and last week sentenced to 5.5 - 6.5 years in prison. #Repressions
https://www.youtube.com/watch?v=4m3DVE0JUec

@dump_stack @kravietz 3) Most importantly, meme figures are an interesting thing to watch, because they're canaries in the coal mine. For example, see how quickly Kuraev lost his status as "anti-sect expert" when he went like "the Jehova's Witnesses are annoying fuckwits, but they don't deserve prisons." Watch how your government reacts to them and you'll know where the arrests are headed.

Two Yorkshire lasses saved orphaned ducklings near a busy road by using a YouTube video of a mother duck calling to get the birbs to follow them to safety 😁 🦆

https://www.bbc.co.uk/news/uk-england-leeds-57009807

Lindenfors, Wartel and Lind on Dunbar's number: https://royalsocietypublishing.org/doi/10.1098/rsbl.2021.0158

My favorite part: "‘Dunbar's number’ is often cited1, has had great impact in popular culture (e.g. it featured prominently in Malcolm Gladwell's book Tipping point [21]) and has had consequences such as the Swedish Tax Authority restructuring their offices to stay within the 150-person limit [22], with the implicit but hopefully unintended assumption that their employees have neither family nor friends outside work."

Hm, some really interesting international developments lately. Exhibit one: Ukraine gives its slot (one of it's slots? Haven't looked into it deeply) in the UN Permanent Forum On Indigenous Issues to an Erzyan elder: (timestamp 1:53:10, http://webtv.un.org/watch/3rd-meeting-united-nations-permanent-forum-on-indigenous-issues-unpfii-twentieth-session-19-30-april-2021/6249705719001/)

Exhibit 2: the rather famous Ukrainian rock band Komu Vniz does a song in the Erzyan language: https://www.youtube.com/watch?v=YCcOQS1I7Pw&t=1s

@requiem @thegibson If I may be allowed to be pedantic here, I ask that my words be considered with some gravity.

The issue isn't static logic. The issue is divorcing instruction decoding from instruction set design to attain performance goals not originally built into the ISA.

It takes, for example, several clock cycles just to decode x86 instructions into a form that can then be readily executed. Several clocks to load the code cache. Several clocks to translate what's in the code cache into a pre-decoded form in the pre-decode cache. Several clocks to load a pre-decode line into the instruction registers (yes, plural) of the instruction fetch unit. A clock to pass that onto the first of (I think?) three instruction decode stages in the core. Three more clocks after that, you finally have a fully decoded instruction that the remainder of the pipelines (yes, plural) can potentially execute.

Of course, I say potentially because there's register renaming happening, there's delays caused by waiting for available instruction execution units to become available in the first place, there's waiting for result buses to become uncontested, ...

The only reason all this abhorrent latency is obscured is because the CPU literally has hundreds of instructions in flight at any given time. Gone are the days when it was a technical achievement that the Pentium had 2 concurrently running instructions. Today, our CPUs, have literally hundreds.

(Consider: a 7-pipe superscalar processor with 23 pipeline stages, assuming no other micro-architectural features to enhance performance, still offers 23*7=161 in-flight instructions, assuming you have some other means of keeping those pipes filled.)

This is why CPU vendors no longer put cycle counts next to their instructions anymore. Instructions are pre-decoded into short programs, and it's those programs (strings of "micro-ops", hence micro-op caches, et. al.) which are executed by the core on a more primitive level.

Make no mistake: the x86 instruction set architecture we all love to hate today has been shambling undead zombie for decades now. RISC definitely won, which is why every x86-compatible processor has been built on top of RISC cores since the early 00s, if not earlier. Intel just doesn't want everyone to know it because the ISA is such a cash cow these days. Kind of like how the USA is really a nation whose official measurement system is the SI system, but we continue to use imperial units because we have official definitions that maps one to the other.

Oh, but don't think that RISC is immune from this either. It makes my blood boil when people say, "RISC-V|ARM|MIPS|POWER is immune."

No, it's not. Neither is MIPS, neither is ARM, neither is POWER. If your processor has any form of speculative execution and depends on caches for maintaining instruction throughputs, which is to say literally all architectures on the planet since the Pentium-Pro demonstrated its performance advantages over the PowerPC 601, you will be susceptible to SPECTRE. Full stop. That's laws of physics talking, not Intel or IBM.

Whether it's implemented as a sea-of-gates in some off-brand ASIC or if it's an FPGA, or you're using the latest nanometer-scale process node by the most expensive fab house on the planet, it won't matter -- SPECTRE is an artifact of the micro-architecture used by the processor. It has nothing whatsoever to do with the ISA. It has everything to do with performance-at-all-costs, gotta-keep-them-pipes-full mentality that drives all of today's design requirements.

I will put the soapbox back in the closet now. Sorry.